1. Field of the Invention
The present invention relates to a semiconductor chip mounting substrate, a semiconductor chip mounting body, a semiconductor chip stacked module, and a semiconductor chip mounting substrate manufacturing method.
2. Related Art of the Invention
There has been growing demand for size reduction, thickness reduction, and integration degree increase in various semiconductor chips used in an electronic device along with size reduction, performance increase, and density increase in electronic devices.
High-density packaging technologies as typified by MCM, MCP, and the like are also introduced into the fields of memory, PC Card, and the like. An example of the introduction is known as a semiconductor chip stacked module in which semiconductor chips as bare chips are stacked on a mother board (see, e.g., International Publication WO 2006/095703).
A conventional semiconductor stacked module will be described below.
FIG. 24(A) is a side view showing a configuration of a semiconductor stacked module, and FIG. 24(B) is an exploded perspective view schematically showing the structure of the semiconductor stacked module.
As shown in FIG. 24(A), a semiconductor stacked module 100 is formed by stacking a plurality of semiconductor chip mounting bodies 120, each having semiconductor chips 121 mounted on each surface of a substrate 122, on a mother board 110 for external connection.
As shown in FIG. 24(B), in each semiconductor chip mounting body 120, the semiconductor chips 121 are provided in a pair on the substrate 122. The substrate 122 has a configuration in which electrodes are inserted in a film of resin such as polyimide. Electric wires of each semiconductor chip 121 are led out from a bonding surface between the semiconductor chip 121 and the substrate 122 as wiring patterns, and the wiring patterns are formed as a circuit electrode 124 in the substrate.
A connection region 123 is further formed between the circuit electrodes 124. The connection region 123 is a region where electrodes led from the circuit electrodes 124, through holes, or the like are formed. These portions are exposed to the outside. Note that the surface of the substrate 122 including the surfaces of the circuit electrodes 124 is covered with an insulating film, and each semiconductor chip mounting body 120 does not electrically connect with the other semiconductor chip mounting bodies 120 at a portion other than the connection region 123.
A pair of alignment marks 125 is provided on the substrate 122. The alignment marks 125 are used to align the connection regions 123 at the time of stacking of the semiconductor chip mounting bodies 120. The alignment marks 125 are formed on the substrate 122 by patterning such as etching or plating simultaneously with formation of the circuit electrodes 124 and the electrodes in the film in the connection region 123.
The plurality of semiconductor chip mounting bodies 120 as described above are fabricated and are sequentially stacked while checking the positions of the alignment marks 125 using a recognizer and automatically aligning the semiconductor chip mounting body 120. The connection regions 123 are brought into pressure contact with one another, and the electrodes or through holes in the connection regions 123 are electrically connected in a thickness direction.
With this process, the semiconductor chip mounting bodies 120 at respective layers are connected, and one stacked module is finished. In the example shown in FIG. 24(A), the semiconductor chip mounting bodies 120 are configured to have the same dimensions. Due to the thicknesses of the semiconductor chips 121, when the semiconductor chip mounting bodies 120 are stacked, one located higher is more inclined. In an actual example, the semiconductor chip mounting bodies 120 are designed in consideration of the thicknesses of the semiconductor chips 121 such that one located higher has the circuit electrodes 124 with larger widths and a wider interval between the pair of semiconductor chips 121. With this configuration, in the stacked module, the semiconductor chip mounting bodies 120 are stacked such that the surfaces of each of the semiconductor chips 121 facing each other are in pressure contact with each other, as shown in FIG. 25.
A wholly dense semiconductor memory can be obtained by using, e.g., a RAM as the semiconductor chip 121 in a semiconductor stacked module as described above. For example, the capacity of an SD Memory Card can be increased.
Size reduction and thickness reduction in the semiconductor chip mounting bodies 120 constituting a semiconductor stacked module are required for size reduction and density increase in modules.
Especially if a ready-made product with predetermined specs and dimensions (e.g., with a uniform thickness of 50 μm) is used as the semiconductor chip 121, thinning of the substrate 122 is effective in thinning a module. Currently available substrates are 30 to 50 μm in thickness. Size reduction and density increase in a semiconductor stacked module are expected to be achieved by thinning the substrate 122 to less than the range.
However, use of a substrate thinner than ever before in a semiconductor stacked module suffers the problem below.
In the fabrication of the semiconductor chip mounting body 120, mounting of the semiconductor chips 121 on the substrate 122 is performed by flip-chip mounting.
If a base material thinner than a currently used one is used for the substrate 122 at this time, the substrate 122 may expand or deform due to heat treatment. Since the circuit electrodes 124 and the electrodes in the connection region 123, which are electrodes formed in the film of the substrate 122, are configured to have a large area at the substrate surface, they are not affected by the heat treatment. In contrast, since the alignment marks 125 are small structures independent of the circuit electrodes 124 and other portions, they are positionally shifted from the initial positions at the time of formation due to the deformation in the substrate 122.
If the alignment marks 125 are positionally shifted, the connection regions 123 cannot be aligned with one another at the time of stacking of the semiconductor chip mounting bodies 120.
As described above, ensuring of alignment of the semiconductor chip mounting bodies 120 to be stacked has become an issue for size reduction and density increase in a semiconductor stacked module.